A Feasibility Study of Hardware Speculative Parallelization in Snoop-Based Multiprocessors

Run-time parallelization is a technique for par-allelizing programs with data access patterns dif-cult to analyze at compile time. In this paper we examine the hardware implementation of a run-time parallelization scheme, called speculative parallelization, on snoop-based multiproces-sors. The implementation is based on the idea of embedding dependence checking logic into the cache controller of the snooping caches. We will present the design of the hardware checker and evaluate the eeectiveness of the design on paral-lelizing DOALL and DOACROSS loops at run-time. The simulation results show that the checkers can help detect hazards sooner than software implementations without slowing down the caches.